Memory using distributed data line loading

Details Memory using distributed data line loading Memory using distributed data line loading

1989-04-21

1990-05-22

Moffitt, James W.

Static information storage and retrieval

Addressing

Plural blocks or banks

G11C 800

Patent

active

049282689

ABSTRACT:
A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.

REFERENCES:
patent: 4698788 (1987-10-01), Flannagan et al.
patent: 4760561 (1988-07-01), Yamamoto et al.
patent: 4807191 (1989-02-01), Flannagan

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