Memory unit with pipelined cycle of operations

Details Memory unit with pipelined cycle of operations Memory unit with pipelined cycle of operations

1979-04-09

1981-02-24

Malzahn, David H.

Boots, shoes, and leggings

G06F 930

Patent

active

042531470

ABSTRACT:
A memory unit is disclosed for receiving and executing instructions transmitted along buses. The memory unit includes registers and control logic that permit it to accept a second instruction from the bus and begin error checking procedures on the second instruction, all while completing the execution of a first instruction.

REFERENCES:
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patent: 4025771 (1977-05-01), Lynch, Jr. et al.
patent: 4040030 (1977-08-01), Cassonnet
patent: 4040031 (1977-08-01), Cassonnet

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