Memory unit with compensating delay circuit corresponding to a d

Details Memory unit with compensating delay circuit corresponding to a d Memory unit with compensating delay circuit corresponding to a d

1989-04-03

1991-10-01

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

050540025

ABSTRACT:
A memory unit includes an array of memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A decoder receives an address signal at a timing which follows an occurrence of a clock signal by a given time t1. The address signal is in synchronism with the clock signal. The clock signal has a preset period t0. The decoder decodes the address signal into a word signal and outputs the word signal at a timing which follows the reception of the address signal by a given time t2. A delay device delays the clock signal by a preset time "t" and thereby converts the clock signal into a control signal. An access to a word of the memory cells is performed via one of the word lines in accordance with the word signal at a timing determined by the control signal. The bit lines are precharged at a timing determined by the control signal. The preset time "t" is longer than a sum of the time t1 and t2 but shorter than a half of the period t0.

REFERENCES:
patent: 4905192 (1990-02-01), Nogami et al.

Affiliated with

Also associated with

Rating

Memory unit with compensating delay circuit corresponding to a d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory unit with compensating delay circuit corresponding to a d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory unit with compensating delay circuit corresponding to a d will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1760408