Memory unit for connection to central processor unit and interco

Details Memory unit for connection to central processor unit and interco Memory unit for connection to central processor unit and interco

1974-04-17

1977-04-05

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 300

Patent

active

040165418

ABSTRACT:
In order to incorporate a very high speed memory subsystem into a computer system utilizing unified bus architecture, memory control apparatus associated with the very high speed memory is provided with a first port communicating directly with a system central processor and a second port interfacing with the unified bus. The memory control apparatus may include means for systematically refreshing volatile high speed memories. Multiple processor systems may be realized by taking advantage of the dual port characteristics of the very high speed memory subsystems associated with each central processor.

REFERENCES:
patent: 3810114 (1974-05-01), Yamada et al.
patent: 3828325 (1974-08-01), Stafford et al.
patent: 3845425 (1974-10-01), Clements et al.

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