Memory unit delay-compensating circuit

Details Memory unit delay-compensating circuit Memory unit delay-compensating circuit

1991-04-15

1993-05-04

Dixon, Joseph L.

Static information storage and retrieval

Addressing

Sync/clocking

365211, 365212, G11G 704

Patent

active

052087832

ABSTRACT:
A memory unit includes an array of memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A decoder receives an address signal at a timing which follows an occurrence of a clock signal by a given time t1. The address signal is in synchronism with the clock signal. The clock signal has a preset period t0. The decoder decodes the address signal into a word signal and outputs the word signal at a timing which follows the reception of the address signal by a given time t2. A delay device delays the clock signal by a preset time "t" and thereby converts the clock signal into a control signal. An access to a word of the memory cells is performed via one of the word lines in accordance with the word signal at a timing determined by the control signal. The bit lines are precharged at a timing determined by the control signal. The preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0.

REFERENCES:
patent: 4162540 (1979-07-01), Ando
patent: 4905192 (1990-02-01), Nogami et al.
patent: 4918657 (1990-04-01), Takahashi

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