Patent
1977-02-25
1978-07-18
Wojciechowicz, Edward J.
357 54, 357 55, H01L 2978
Patent
active
041019210
ABSTRACT:
In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, the gate insulating layer has a pair of thick gate guarding portions which exist on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions, and a surface impurity concentration per square centimeter of the semiconductor layer under the thick gate guarding portions is different from a surface impurity concentration per square centimeter of the semiconductor layer under the tin memory portion. The voltage difference between the threshold voltages of the semiconductor device at the memorized state and at the non-memorized state can be increased, and the read-out voltage of the semiconductor device can be reduced. The circuit design is simplified.
REFERENCES:
patent: 3877055 (1975-04-01), Fisher et al.
patent: 4011576 (1977-03-01), Uchida et al.
Inoue Ken-ichi
Mochizuki Hidenobu
Ohtsu Takaji
Shimada Takashi
Yamaguchi Jiro
Sony Corporation
Wojciechowicz Edward J.
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