Memory transistor gate oxide stress release and improved...

Details Memory transistor gate oxide stress release and improved... Memory transistor gate oxide stress release and improved...

2007-06-06

2008-12-30

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read only systems

Semiconductive

C365S189070, C365S189170

Reexamination Certificate

active

07471541

ABSTRACT:
Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

REFERENCES:
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patent: 5717625 (1998-02-01), Hasegawa et al.
patent: 6049490 (2000-04-01), Kawasumi et al.
patent: 6175535 (2001-01-01), Dhong et al.
patent: 6862242 (2005-03-01), Chen et al.

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