Memory timing circuit employing scaled-down models of bit lines

Details Memory timing circuit employing scaled-down models of bit lines Memory timing circuit employing scaled-down models of bit lines

1988-12-27

1990-05-15

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

36518901, 36518905, 365203, G11C 1140, G11C 1300

Patent

active

049263870

ABSTRACT:
A timing circuit is described for a single phase clocked memory. A plurality of models duplicating a word line, a bit line, a cell, etc., are used in the timing circuit. The bit line model is scaled down compared to the actual bit line, however, in conjunction with the drive to the bit line (scaled up model of the cell), the signal on the bit line model is greater than the actual signal on the bit line in the array during reading. This simplifies the detection circuitry needed in the timing circuit and provides more accurate control signals.

REFERENCES:
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4658158 (1987-04-01), Chau et al.
patent: 4802122 (1989-01-01), Auvinen et al.
patent: 4823319 (1989-04-01), Pfennings

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