Memory timing and control apparatus

Details Memory timing and control apparatus Memory timing and control apparatus

1983-02-14

1988-03-15

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1200

Patent

active

047317388

ABSTRACT:
A memory board can be assembled with one, two or more rows of memory chips to provide a corresponding number of different memory capacities for expanding the capacity of main memory which resides on a basic logic board containing the processing units and other units of a system. The memory board includes a programmable read only memory (PROM) circuit which receives as inputs from the basic logic board a predetermined address portion of each memory address together with memory refresh and timing signals. The PROM circuit is coded in a predetermined manner for generating at its output terminals row address select (RAS) pulse output signals to a row or block of memory chips designated by the predetermined address portion. The pulse widths of the output signals are established by the timing signal applied to an enabling terminal of the PROM.

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Short; K. L., Microprocessors and Programmed Logic, Prentice Hall, 1981, pp. 48, 49.

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