Memory testing device for preventing excessive write and erasure

Details Memory testing device for preventing excessive write and erasure Memory testing device for preventing excessive write and erasure

1993-10-29

1995-05-02

Nguyen, Hoa T.

Excavating

G11C 2900

Patent

active

054126622

ABSTRACT:
A memory testing device having n test channels for simultaneously testing n memories. A pattern generator generates a sequence of test patterns each including a write enable signal, expected value data, write data and an address signal. In each test channel, the write enable signal WE is repeatedly applied via the AND gate to a terminal WE of the corresponding memory under test to write the data thereinto at an address designated by the address signal. Data read out therefrom is compared to the expected value data to produce a comparison result. The comparison result is used to control the AND gate so that when the comparison result indicates coincidence between the compared data, the write enable signal WE is inhibited.

REFERENCES:
patent: 4628509 (1986-12-01), Kawaguchi
patent: 4696004 (1987-09-01), Nakajima et al.
patent: 4775977 (1988-10-01), Dehara
patent: 5099480 (1992-03-01), Murata

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