Static information storage and retrieval – Magnetic bubbles – Guide structure
Patent
1993-12-30
1996-01-02
Beausoliel, Jr., Robert W.
Static information storage and retrieval
Magnetic bubbles
Guide structure
365201, G11C 2900, G11C 700
Patent
active
054816718
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a memory testing deivce and, more particularly, to a memory testing device for performing a read/transfer function test of a memory device having a random access memory (RAM) part and a serial or sequential access (SAM) part, the memory device commonly referred to as a multi-port DRAM or dual port video RAM. This read/transfer function test of the memory device is such that all data stored at addresses of one row address of a RAM part of a memory device under test are transferred from the RAM part to a SAM part at one time, reads out therefrom the transferred data in the SAM part are sequentially read out of the SAM part and are sequentially compared with an expected value. In such a read/transfer function test of a memory device such as a multi-part DRAM or dual port video RAM, in accordance with the present invention, when a failure occurs, data indicating the failure is written into a sub failure analysis memory at the same address as that in the RAM part where the failure bit was stored.
BACKGROUND OF THE INVENTION
A conventional memory testing device will be described with reference to FIGS. 4 through 7. A multi-port DRAM 2, which is a memory under test (hereinafter referred to as MUT), has a RAM part 2a and a SAM part 2b as shown in FIG. 4. The RAM part 2a has an address input terminal A, a control signal input terminal CT and a data I/O terminal D, whereas the SAM part 2b has a clock terminal CLK and a data I/O terminal D. Assuming, for the sake of simplicity, that the RAM part 2a has, for instance, 0 to 255 row addresses and 0 to 255 column addresses, that is, that M=N=255 in FIG. 4, a row address signal and a column address signal each have an 8-bit configuration.
Timing signals, which are fed from main and sub timing generating parts 3a and 3b which form a timing generator 3, are supplied to main and sub pattern generating parts 4a and 4b which form a pattern generator 4. In synchronization with the input timing signal thereto, the main pattern generating part 4a responds to an instruction from an instruction memory, not shown, to generate and apply a control signal, a test pattern TP and an address signal MA for writing the test pattern to the RAM part 2a of the MUT 2. The address signal MA is fetched, as sets of row and column addresses (hereinafter referred to also as a main address), into the RAM part 2a and pattern data is written into or read out from memory cells selected by the main address. In general, a plurality of memory cells are provided at each address so that data of plural bits can be stored as one word, but one memory cell may also be provided. The data read out of the RAM part 2a is input into a main logical comparison part 6a, wherein it is compared with an expected pattern EP that is provided from the main pattern generating part 4a. Upon detecting a disagreement at any bit in the word read out from a certain address, a main failure signal MF=" 1" is immediately generated and fed to a main failure analysis memory 7a. The main failure analysis memory 7a has the same storage space as that of the RAM part 2a and is supplied at its address input terminal A with the same version as the main address signal MA that is applied to the RAM par 2a; hence, the main failure signal MF="1" is written into the memory 7a at the same address as that (a set of row and column addresses concerned) in the RAM part 2a where the word-containing the failure bit in the output from the SAM part 2b had been stored before it was transferred.
Thereafter, test patterns are sequentially written into the RAM part 2a at its all addresses and the same test as mentioned above is repeated; upon each occurrence of a failure bit, the main failure signal MF="1" is written into the main failure analysis memory 7a.
A row address (hereinafter referred to as a transfer row address) of the RAM part 2a from which pieces of data are to be transferred to the SAM part 2b at one time is provided from the main pattern generating part 4a to the RAM part 2a; at the sam
REFERENCES:
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4736373 (1988-04-01), Schmidt
patent: 5062109 (1991-10-01), Ohsima et al.
patent: 5263029 (1993-11-01), Wicklund, Jr.
Advantest Corporation
Beausoliel, Jr. Robert W.
Wright Norman M.
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