Memory testing device

Details Memory testing device Memory testing device

1997-10-02

1999-03-30

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058897860

ABSTRACT:
In a memory testing device of a construction wherein various pieces of pattern data output from a pattern generator are taken out in a desired order and converted into a test pattern signal having a real waveform for application to each pin of a memory under test, the pattern selector provided for each I/O pin of the memory under test comprises plural registers having stored therein pattern selection control signals that designate patterns to be selected, a first multiplexer for selecting that one of the registers designated by a register selection control signal PJ generated by the pattern generator, and a second multiplexer that is controlled by the pattern selection control signal selected by the first multiplexer to select a pattern from the pattern data output from the pattern generator.

REFERENCES:
patent: 5809336 (1998-09-01), Moore et al.
patent: 5815512 (1998-09-01), Osawa et al.

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