Excavating
Patent
1997-05-21
1999-06-01
Nguyen, Hoa T.
Excavating
365201, G11C 2900, G11C 700
Patent
active
059094486
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a memory testing apparatus for testing a memory in the form of an integrated circuit (a semiconductor integrated circuit memory, hereinafter referred to as an IC memory), and particularly, relates to a portion or section of such memory testing apparatus including a failure analysis memory for storing test results of an IC memory.
BACKGROUND OF THE RELATED ART
Storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a lowering of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being lowered, various failure relieving procedures or processes have been taken wherein a failure or defect element is replaced by a substitute or alternative element.
FIG. 12 generally shows an entire circuit arrangement of a prior conventional memory testing apparatus, and FIG. 13 is an illustration of the inside of an IC memory for explaining an analysis method for failure relief. As shown in FIG. 13, an IC memory includes a main element 17 which is a main storage portion, and four substitute elements 18, 19, 20 and 21 disposed around the main element 17 (in this example, at the lower side and the right side of the main element). The main element 17 has, in this example, the total of 64 storage elements in the form of a matrix of 8 rows.times.8 columns. As shown in the figure, rows are denoted by A, B, C, . . . , H, respectively, and columns are denoted by a, b, c, . . . , h, respectively, for brief explanation. Each of intersecting points or areas Aa, Ab, Ac, . . . , Hh of rows and columns of the main element 17 forms a unit element which is a unit storage element of the IC memory.
The substitute elements 18, 19, 20 and 21 are previously provided in the IC chip for a failure relief and each substitute element comprises a plurality of unit storage elements. In this example, four substitute elements are shown. However, the number of substitute elements and the disposed locations in the IC chip may be arbitrarily selected as the case may be.
Assuming that the IC memory shown in FIG. 13 was tested by a memory testing apparatus shown in FIG. 14 to be described later, and as a result, failures or defects were found in, for example, four unit elements Bb, Be, Df and Fe as shown in FIG. 13 by oblique lines, the row B including the failure unit elements Bb and Be, the column f including the failure unit element Df, and the row F including the failure unit element Fe are removed from the main element 17 so that no failure unit element exists in the main element 17.
Then, the substitute element 18 is substituted for the row B, the substitute element 19 is substituted for the row F, and the substitute element 20 is substituted for the column f. In such a way, by replacing a row or rows and/or a column or columns each including one or more failure unit elements by such substitute elements, the IC memory can be relieved such that all of the addresses thereof can be used even if the IC memory has one or more failure unit elements in the main element 17 thereof.
As described above, in order to relieve an IC memory of a failure element or elements, "information for indicating at which address or addresses a failure unit element or elements exist" which is called a failure map is necessary, and hence, as shown in FIG. 12, a memory testing apparatus having a failure analysis memory (failure memory) 16 for storing therein failure information (data) is used.
This memory testing apparatus comprises a timing generator (TMG GEN) 22, a pattern generator (PTN GEN) 23 and a waveform shaping device (WAVE SHAPE) 24 whereby a predetermined test pattern signal is generated and is applied to a memory under test (IC memory under test) MUT to write predetermined data in the memory under test MUT (hereinafter referred to as MUT). The data written in the MUT are read out therefrom later to
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Advantest Corporation
Nguyen Hoa T.
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