Memory testing apparatus

Details Memory testing apparatus Memory testing apparatus

1997-09-18

1998-11-03

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058319891

ABSTRACT:
There is provided a memory testing apparatus which can read out the information of failure memory cells of a tested memory from a failure analysis memory having the same memory capacity as that of a memory under test and can complete in a short time period the process for computing the classified total of the number of memory cell failures occurred. The memory area of the failure analysis memory is subdivided into a plurality of memory blocks, a flag memory having the same number of addresses as the number of the subdivided memory blocks is provided, and an address is assigned to each of the memory blocks. When a failure occurs in one of the memory blocks, a logical "1" indicating failure information is written at an address of the flag memory corresponding to that memory block. After the test is completed, the address of the flag memory where the logical "1" has been written is detected and the contents of the memory block corresponding to the detected address are read out to compute the classified total of the failure information.

REFERENCES:
patent: 4736373 (1988-04-01), Schmidt
patent: 5337318 (1994-08-01), Tsukakoshi et al.

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