Memory tester having memory repair analysis capability

Details Memory tester having memory repair analysis capability Memory tester having memory repair analysis capability

1981-07-15

1984-07-17

Atkinson, Charles E.

Excavating

371 21, G06F 1120

Patent

active

044609973

ABSTRACT:
A memory tester is disclosed for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned first by row and when the number of failures in any row exceeds the number of spare columns that row is flagged for replacement. Next, the columns of failure data are scanned and when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. During the scan of the columns, previously flagged rows are masked such that failures which are to be repaired are not counted. Thereafter, with the flagged rows and column failures masked, the rows are again scanned and individual failures are flagged for replacement by remaining spare rows and columns until all spare rows and columns are used at which point detection of a subsequent failure flags the memory under test as non-repairable.

REFERENCES:
patent: 3995261 (1976-11-01), Goldberg
patent: 3999051 (1976-12-01), Petschauer
patent: 4047163 (1977-09-01), Choate et al.
patent: 4380066 (1983-04-01), Spencer et al.
Mano, Computer System Architecture, Prentice-Hall, Englewood Cliffs, N.J., 1976.
Huber, "The 64K Ram: A Fault-Tolerant Semiconductor Memory Design", Bell Labs Record, vol. 57, No. 7, Jul./Aug. 1979.

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