Memory tester having concurrent failure data readout and memory

Details Memory tester having concurrent failure data readout and memory Memory tester having concurrent failure data readout and memory

1981-08-03

1988-04-05

Harkcom, Gary V.

Excavating

371 21, G06F 1126

Patent

active

047363738

ABSTRACT:
A memory tester for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned, in a first pass, row-by-row and during the first pass scan when the number of failures in any row exceeds the number of spare columns that row is flagged for replacement. Next, in a second pass, the columns of failure data are scanned column-by-column and during the second pass when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. If, during either of the first or second pass, the number of flagged rows or columns, respectively, exceeds a certain number, such as the spare rows or columns, that pass is interrupted and the analysis jumps to the next pass. After all spare rows and columns are used, detection of a subsequent failure flags the memory under test as non-repairable.

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