Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1998-06-11
2000-08-01
Ballato, Josie
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
714723, G01R 3126, G11C 2900
Patent
active
060972068
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a memory testing apparatus provided with a ROM (read only memory) expected value memory, which is capable of testing both a writable/readable memory called RAM (random access memory) and a read only memory called ROM, and to a method of switching the operation mode of the testing apparatus between a RAM test mode and a ROM test mode.
BACKGROUND ART
A memory testing apparatus for testing a writable/readable memory (hereinafter referred to as RAM) generally comprises a timing generator, a pattern generator, a waveform generator, a logical comparator and a failure analysis memory. As is well known, a RAM and a read only memory (hereinafter referred to as ROM) are often formed as a semiconductor integrated circuit element. In the following description, in order to facilitate understanding of the present invention, a case will be discussed in which a memory as constructed in the form of a semiconductor integrated circuit element (hereinafter referred to as IC memory) is tested by such memory testing apparatus, but it is to be noted that the memory testing apparatus can also test memories other than IC memories.
A pattern generator is operative, in response to a reference clock (operating clock) fed from the timing generator, to generate address pattern data, test pattern data, control signals and the like which are to be applied to an IC memory to be tested (memory under test), and also to generate expected value pattern data and the like which are to be supplied to the logical comparator.
An IC memory to be tested (commonly called MUT (memory under test)) is controlled in writing of a test pattern signal therein or reading of a test pattern signal therefrom by application of a control signal thereto. Specifically, when a writing control signal is applied to the IC memory under test, a test pattern signal is successively written in the IC memory under test at an address thereof specified by an address pattern signal, and when a reading control signal is applied to the IC memory under test, the test pattern signal previously written in the IC memory under test is successively read out thereof at an address specified by an address pattern signal.
A response output signal read out of the IC memory under test (hereinafter, also referred to simply as memory under test) is supplied to the logical comparator where it is logically compared with an expected value pattern data outputted from the pattern generator. If a result of the comparison indicates that there is an anti-coincidence or a mismatch therebetween, the logical comparator outputs a defective signal representing the anti-coincidence, namely, so-called failure data. Usually, as the failure data is outputted logical "1" which is a high logical level (logic H). By contrast, if a result of the comparison indicates that they coincide with each other, the logical comparator outputs a conforming or defectless signal representing the coincidence, namely, so-called pass data. Since the failure data is represented by logical "1", as the pass data is outputted logical "0" which is a low logical level (logic L). The failure data is fed to and stored in the failure analysis memory.
The failure analysis memory has the same operating rate or speed and storage capacity as those of the memory under test, and the same address pattern signal as that applied to the memory under test is applied to the failure analyses memory. In addition, the failure analysis memory is initialized prior to the start of a test. For example, when initialized, the failure analysis memory has data of logical "0s" written in all of the addresses thereof. Every time a failure data is generated from the logical comparator during a test of a memory under test, a failure data of logical "1" is written in the address of the failure analysis memory specified by the address pattern signal. That is, in a memory cell of the failure analysis memory having the same address as that of the failure memory cell of the memory under test is written the failure dat
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patent: 5835428 (1998-11-01), Kobayashi
Advantest Corporation
Ballato Josie
Kobert Russell M.
Lathrop David N.
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