Memory tester

Details Memory tester Memory tester

1989-08-25

1991-10-29

Atkinson, Charles E.

Excavating

371 211, G01R 3128

Patent

active

050621092

ABSTRACT:
In a memory tester in which data read out of an address of a memory under test, specified by a pattern generator, is compared with an expected value and the result of comparison is written into a failure analysis memory at the address corresponding to that of the memory under test from which the data was read out, the output address of an address pointer which is incremented or decremented upon each application of a clock and the address from the pattern generator are selectively applied to the failure analysis memory. In the case of testing a memory which has an internal address generating function, the address from the address pointer is provided to the failure analysis memory. A cycle delay circuit is provided by which the address to be provided from the pattern generator to the failure analysis memory is delayed by a desired number of cycles in synchronism with the clock, and the address to be applied to the failure analysis memory is delayed by the same number of cycles as that for which the data read out of the memory under test is delayed.

REFERENCES:
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4783785 (1988-11-01), Hanta
patent: 4788684 (1988-11-01), Kawaguchi et al.

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