Memory tester

Details Memory tester Memory tester

1991-01-03

1993-05-25

Beausoliel, Jr., Robert W.

Excavating

371 27, G11C 2900

Patent

active

052146545

ABSTRACT:
In a memory tester for testing memories of the type having a polarity inversion feature there are provided a bit select circuit for selecting from an address generated by an address generator a plurality of bits necessary for a logical expression expressing a polarity-inverted data storage area of the memory under test and a bit register circuit for storing bit data which is used to supply the bit select circuit with a select signal for specifying bits to be selectively output. The bits selectively output by the bit select circuit are used as an address for reading out a polarity inversion control signal from an area inversion memory. A polarity inverter, supplied with test data signal from a data generator, outputs the test data intact or after inverting its polarity in accordance with the logic of the polarity inversion control signal, and the output data is written into the memory under test.

REFERENCES:
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4835774 (1989-05-01), Ooshima et al.
patent: 4888772 (1989-12-01), Tamigawa
patent: 4958346 (1990-09-01), Fujisaki
patent: 4998025 (1991-03-01), Watanabe

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