Memory test system

Details Memory test system Memory test system

1997-06-17

1999-05-11

Canney, Vincent P.

Excavating

G11C7/00

Patent

active

059035765

ABSTRACT:
A memory test system is to perform two or more comparison operations within one test cycle. The memory test system includes a pattern generator for generating test data patterns to be supplied to the memory device under test, a data selector for providing the test data patterns in a parallel fashion at a plurality of ports, a test data multiplexer for selecting one of the test data patterns at the plurality of ports to supply a plurality of test data patterns to the memory device in a series fashion within each of the predetermined test cycle, an expected value select circuit for selectively providing the test data pattern as expected value data in a parallel fashion, and a logic comparator for receiving, in a parallel fashion, an output signal from the memory device under test generated as a result of the test data patterns and comparing, in parallel, the output signals with the expected value data from the expected value select circuit.

REFERENCES:
patent: 5574684 (1996-11-01), Tomoeda
patent: 5579272 (1996-11-01), Uchida

Affiliated with

Also associated with

Rating

Memory test system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory test system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory test system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-251535