Memory test pattern generator

Details Memory test pattern generator Memory test pattern generator

1986-12-10

1989-01-10

Fleming, Michael R.

Excavating

G01R 3128

Patent

active

047978864

ABSTRACT:
A memory test pattern generator generates a memory test pattern by reading out data from a microinstruction program memory according to an instruction of an address counter and causing an address generator, a data generator and a timing generator to generate an address, data and a timing signal, respectively, according to the read-out data. To test a memory device, which has internal address generation means and is capable of address accessing by a clock signal, data representing the number of times of internal address is set in a repeat register. When a signal representing the internal address mode is read out from the microinstruction program memory, the increment of the address counter is stopped by a repeat controller, and the operation in the address and data generators is inhibited. At the same time, a timing set controller and an internal address generator are rendered operative, whereby an internal address is generated. An address multiplexer replaces predetermined bits of a fixed address generated from the address, generator with the internal address. Further, according to the internal address fixed data of the data generator is selectively passed bit by bit through a data multiplexer. Further, a timing set controller produces timing data before, during and after the internal address generation according to a timing reference signal from a repeat controller.

REFERENCES:
patent: 4300234 (1981-11-01), Maruyama
patent: 4460999 (1984-07-01), Schmidt
patent: 4555663 (1985-11-01), Shimizu
patent: 4631724 (1986-12-01), Shimizu
patent: 4701918 (1987-10-01), Nakajima
patent: 4701919 (1987-10-01), Naitol

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