Memory test circuit

Details Memory test circuit Memory test circuit

1986-03-31

1987-08-11

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

371 21, G01R 3126, G11C 2900

Patent

active

046864563

ABSTRACT:
A memory test circuit in which test data is simultaneously written into plural memory cells of a semiconductor memory device and then subsequently read from the plural memory cells to assure reliable operation of the memory device. A logical sum and a logical product are formed of the test data read out from the plural memory cells. The logical product and the logical sum are subjected to an exclusive-or operation, the result of which is indicative of whether or not the test data was correctly written into the memory cells.

REFERENCES:
patent: 3351905 (1967-11-01), Kramer
patent: 3420991 (1969-01-01), Ling
"A 90ns 1Mb DRAM with Multi-Bit Test Mode" ISSCC 85, pp. 240-241 M. Kumanoya, et al. 2/15/85.

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