Memory test circuit

Details Memory test circuit Memory test circuit

1996-02-28

1997-06-03

Beausoliel, Jr., Robert W.

Excavating

371 212, 371 213, 371 225, G11C 2900

Patent

active

056362250

ABSTRACT:
It is an object to reduce circuit scale and increase operation speed of a memory test circuit which performs a memory test according to the ping-pong pattern. An address signal of a remarked cell is generated by an LFSR (76) and address signals for other cells are generated by an LFSR (75). The LFSR (76) updates the generated address signal every time the LFSR (75) generates one cycle of address signals. The address signals of the LFSR's (75, 76) are alternately switched by a selector circuit (78) and outputted to a RAM (2A).

REFERENCES:
patent: 5101409 (1992-03-01), Hack
patent: 5198709 (1993-03-01), O'Connell
patent: 5258986 (1993-11-01), Zerbe
patent: 5323355 (1994-06-01), Kato
patent: 5327363 (1994-07-01), Akiyama
patent: 5471482 (1995-11-01), Byers et al.

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