Memory systems and related error detection and correction appara

Details Memory systems and related error detection and correction appara Memory systems and related error detection and correction appara

1987-12-14

1989-08-29

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

048624624

ABSTRACT:
Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having single byte parallelism, each module having a section with a plurality of bit parallelism for storing SEC-DED codes related to the information stored in the module and wherein a fast memory, addressed with the information codes and the related SEC-DED codes read out from a memory module produces an information output code, corrected as a function of the SEC-DED code, a parity check bit for the corrected information code, and further bits indicative of a corrected single error and a multiple error which cannot be corrected.

REFERENCES:
patent: 3814921 (1974-06-01), Nibby et al.
patent: 4058851 (1977-11-01), Scheuneman
patent: 4646304 (1987-02-01), Fossati et al.

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