Memory systems and methods of making the same

Details Memory systems and methods of making the same Memory systems and methods of making the same

2002-03-07

2003-07-15

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Hardware for storage elements

C365S063000, C365S072000

Reexamination Certificate

active

06594171

ABSTRACT:

TECHNICAL FIELD
This invention relates to memory systems and methods of making the same.
BACKGROUND
In general, a memory system includes a plurality of memory elements that are arranged in an array of individually accessible cells. Many different memory systems are available for different applications. For example, volatile memories (e.g., dynamic random access memories), which require a continuous source of power to retain their contents, provide high storage capacity and versatile customization options for microprocessor-based applications. Nonvolatile memories (e.g., read only memories and programmable logic arrays), which do not require a continuous source of power to retain their contents, provide relatively lower storage capacity and limited customization options.
Nonvolatile memories typically store information in one of two ways. In particular, a nonvolatile memory may store a charge or may store a unique physical structure. A charge-storing nonvolatile memory uses a relatively small electrical current to store a charge at a memory element location. A structure-changing memory, on the other hand, typically uses a large electrical current to change the physical structure of a memory element (e.g., a customization or a chalcogenide memory element). In both charge-storing and structure-changing nonvolatile memories, an access device (e.g., access transistor or an access diode) typically provides individual access to an associated memory element. During a read operation, all of the access devices in the memory array are turned off except the access device associated with the particular memory cell to be read.
Three-dimensional memory systems have been proposed to increase the memory cell packing density. For example, U.S. Pat. No. 5,640,760 describes a memory system in which multiple printed circuit boards, each supporting a plurality of electronic component packages (e.g., memory chip packages), are stacked together to form a three-dimensional array of interconnected electronic components. The stack is sliced through to form bars. The pins of the electronic component packages are electrically connected to the side surfaces of the bars by tracks on the printed circuit boards. The packages are connected to each other by side surfaces of the bars. The bars then are sliced through to obtain unit blocks of stacked packages.
SUMMARY
The invention features a memory system that includes multiple memory layers that may be identical when manufactured and may be readily customized before or after the layers are arranged into a three-dimensional stack so that data may be sent to or retrieved from individual layers (either serially or in parallel) independently of the other layers.
In one aspect, the invention features a memory system that includes a stack of N memory layers. Each memory layer includes an array of memory cells each coupled to a common data line, and a set of N input/output (I/O) lines each coupled to the common data line. Only one of the set of N I/O lines provides an electrical communication path to the common data line. The memory system also includes a set of N electrical connectors each electrically connecting a respective output node to a respective set of N corresponding I/O lines. Each set of corresponding I/O lines consists of one I/O line from each of the N memory layers.
Embodiments in accordance with this aspect of the invention may include one or more of the following features.
Preferably, only one I/O line of each set of corresponding I/O lines provides the electrical communication path to the common data line of the corresponding memory layer.
In some embodiments, one of the N I/O lines of each memory layer comprises a shorted customization element and each of the remaining N−1 I/O lines of each memory layer comprises an original, unmodified customization element. For example, each of the customization elements may comprise an element that is characterized originally by a relatively high electrical resistance.
In other embodiments, one of the N I/O lines of each memory layer comprises an original, unmodified customization element and each of the remaining N−1 I/O lines of each memory layer comprises a blown (or electrically open) customization element. For example, each of the customization elements may comprise an element that is characterized originally by a relatively low electrical resistance.
In another aspect, the invention features a method of manufacturing a memory system. In accordance with this inventive method, N of the above-described memory layers are received. The N memory layers are arranged into a stack. Each of a set of N output nodes are electrically connected to a respective set of N corresponding I/O lines, wherein each set of corresponding I/O lines consists of one I/O line from each of the N memory layers.
Embodiments in accordance with this aspect of the invention may include one or more of the following features.
In some embodiments, each of the I/O lines comprises a customization element that is characterized by a relatively high electrical resistance, and the step of customizing a memory layer comprises shorting the customization element corresponding to the I/O line providing the electrical communication path to the common data line. The step of shorting the customization element may comprise applying a voltage across the customization element. The step of shorting the customization element may comprise illuminating the customization element to be shorted while the voltage is being applied to increase electrical conduction through the illuminated customization element. In some embodiments, the step of shorting the customization element may comprise providing an oxidizing atmosphere near the customization element to be shorted while the voltage is being applied.
In other embodiments, each of the I/O lines comprises a customization element that is characterized by a relatively low electrical resistance, and the step of customizing a memory layer comprises blowing the customization elements of all I/O lines except the I/O line providing the electrical communication path to the common data line. The step of blowing the customization elements may comprise applying a voltage across the customization elements. The step of blowing the customization elements may comprise illuminating the customization elements to be blown while the voltage is being applied to increase electrical conduction through the illuminated customization elements. In some embodiments, the step of blowing the customization elements may comprise providing an oxidizing atmosphere near the customization element to be shorted while the voltage is being applied.
In some embodiments, each of the memory layers is customized before the memory layers are arranged into a stack. In other embodiments, each of the memory layers is customized after the memory layers are arranged into a stack.
In another aspect, the invention features a method of manufacturing a memory system. In accordance with this inventive method, N memory layers are received. Each memory layer comprises an array of memory cells each coupled to a common data line, and a set of N input/output (I/O) lines each coupled to the common data line and including a respective customization element. Each of the memory layers is customized by applying a voltage across and illumination to a selected subset of customization elements so that only one of the set of N I/O lines of each memory layer provides an electrical communication path to the common data line.
The applied illumination preferably increases electrical conduction through the illuminated customization elements. In some embodiments, the applied illumination is dithered over one or more of the selected subset of customization elements, and electrical signals induced by illumination in one or more of the selected subset of customization elements are sensed. The illumination may be aligned over one or more of the selected subset of customization elements based upon the sensed illumination-induced electrical signals.


REFERENCES:
patent: 5008729 (199

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