Static information storage and retrieval – Hardware for storage elements
Reexamination Certificate
1999-08-27
2001-04-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Hardware for storage elements
C365S063000, C361S728000, C439S955000
Reexamination Certificate
active
06215686
ABSTRACT:
TECHNICAL FIELD
The present claimed invention relates to the field of memory storage systems. More particularly, the present invention relates to a memory storage system that includes a memory module on which memory devices are disposed.
BACKGROUND ART
Recent computer systems require faster microprocessors. These computer systems which require fast microprocessors require high memory bandwidth and high memory component capacity. This is particularly true in systems that contain multiple fast microprocessors.
In order to meet the demands of systems containing multiple fast microprocessors, some recent prior art memory modules include up to eighteen memory components on each memory module. These memory systems typically use Dual Inline Memory Modules (DIMMs) aligned in parallel. Typically, each DIMM includes memory components that are Dynamic Random Access Memory (DRAM) semiconductor devices or Synchronous Dynamic Random Access Memory (SDRAM) devices. At slower speeds, these prior art memory modules function adequately. However, at speeds of 200 megahertz and more, signal distortion occurs. This signal distortion causes ringing and edge rate slowdown. In some cases, the signal distortion results in insufficient signal to transfer data.
Recent attempts to meet the demands of systems containing multiple fast microprocessors include architectures that use data switching. Such systems include Field Effect Transistors (FET) devices that operate as switches located on each memory module. These FET switches, in effect, switch off individual memory modules such that only one or two memory modules are transmitting data at any one time. This significantly reduces signal distortion.
Memory modules that include FET switches located on each memory module are effective in reducing signal distortion. However, such memory modules are large and are expensive to manufacture. The inclusion of multiple FET switches adds cost and increases the required size of each memory module. Also, the connection scheme is complicated by the need to couple each data line to one or more FET. This results in a memory module that is complex and that is expensive to manufacture.
Prior art memory modules typically include terminal resistors located on each memory module. These terminal resistors couple to each data line. The terminal resistors take up valuable space on each memory module. Also, the terminal resistors increase the manufacturing cost of the memory module. In addition, such prior art memory modules typically include Series Stub Termination Logic (SSTL) which takes up valuable space on each memory module and increases the manufacturing cost of the memory module.
What is needed is a memory system that has a high memory component capacity and a high data bandwidth while minimizing distortion. Also, a memory system is needed that meets the above requirements and that includes a memory module that is inexpensive to manufacture. In addition, a memory system is needed that meets the above requirements and that includes a memory module that is smaller than prior art memory modules that include FET switches. The present invention provides an elegant solution to the above needs.
DISCLOSURE OF THE INVENTION
The present invention provides a memory system and memory module that has a high memory component capacity and a high data bandwidth while minimizing distortion. This is achieved using a memory system that includes data switching but which does not include FET switches for data switching on each memory module. Also, individual memory modules do not include terminal resistors for data lines. This results in a memory module that is inexpensive to manufacture and that is smaller than prior art memory modules that include FET switches.
A memory system that includes switches for controlling data transfer is disclosed. In one embodiment, the memory system includes a memory controller that is coupled to a motherboard. Data switches are also disposed on the motherboard and are selectively coupled to the controller. Receptacles that are adapted to receive a memory module are coupled to the memory controller. The memory system also includes resistors that are coupled to Each connector receptacle for terminating data signals.
The memory system also includes address/control buffers disposed on the motherboard that buffer address and control signals. The use of multiple address/control buffers provides the necessary bandwidth so as to allow for fast access and control of memory components.
In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. This allows for high-speed operation while minimizing distortion and interference between adjoining and nearby memory modules due to radio frequency interference.
In one embodiment, each memory module includes twenty memory components. However, memory modules are adapted to be configured with fewer or more memory components on a given memory module. In one alternate embodiment, memory modules having forty memory components on each memory module are disclosed.
In one embodiment, the memory system of the present invention includes eight memory modules that use Double Data Rate (DDR) SDRAM memory components. The eight memory modules are used in pairs. When 64 Mbit, 128 Mbit or 256 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).
The memory system of the present invention includes resistors mounted on the motherboard and the same set of resistors is used to terminate data lines of multiple memory modules. Because only two memory modules are active at any time, only a sufficient number of resistors to terminate two memory modules is required. Thus, the memory system of the present invention requires fewer resistors than prior art memory systems that include memory modules that have resistors for data termination on each memory module (a full set of resistors is required on each prior art memory module). Because fewer resistors are required, the memory system of the present invention is less expensive than prior art memory systems that include memory modules that have resistors for data termination on each memory module.
By using switches that are placed on the motherboard, the memory system of the present invention achieves a shorter circuit than that of prior art memory systems that include switches located on each memory module. That is, by placing the switches on the motherboard, there is no need to drive the connector receptacle and the circuitry on each memory module that leads to a switch as is required by prior art memory modules that include switches located on each memory module. In addition, by using switches placed on the motherboard, system performance becomes more predictable. Any number of DIMMs (usually 1 to 4) can be placed in the memory system without affecting performance since the switches isolate unused DIMM connectors from the system. This allows for less performance variation, resulting in the ability to operate at the noted higher frequencies.
It is important to match the amount of memory to customer needs. In prior art systems, each time memory is added via a new DIMM, performance of the memory signal transmission is impacted by the placement of this additional load on the transmission system. At slower speeds, this can be tolerated. However, at higher speeds, this performance variation can not be tolerated. The present invention eliminates this variation by placing switches on the motherboard. Thus, in the present invention, the load on the controller is the same irrespective of the number of DIMMs in the system. This allows for operation at higher frequencies since the loading impact on the controller is reduced.
As previously discussed, the present invention includes switches placed on the motherboard. Thus, there is no need to place switches on each memory module. Because the memory modules of the present invent
Deneroff Martin M.
McCall David Leo
McCracken David Edward
Sarocky Kenneth M.
Ho Hoai V.
Nelms David
Silicon Graphics Inc.
Wagner , Murabito & Hao LLP
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