Memory system with multiple addressing and control busses

Details Memory system with multiple addressing and control busses Memory system with multiple addressing and control busses

1998-04-14

1999-02-09

Le, Vu A.

Static information storage and retrieval

Interconnection arrangements

365 52, G11C 700

Patent

active

058703250

ABSTRACT:
A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.

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