Memory system with built in parity

Details Memory system with built in parity Memory system with built in parity

1983-01-03

1985-07-09

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

045286663

ABSTRACT:
A memory apparatus including an array of storage elements connected to several addressing lines for selectively connecting a group of the storage elements to multiple data lines. The memory apparatus further includes a parity circuit connected to the data lines and storage elements for selectively generating parity to designate the validity of the selected group of data connected in the portion of storage elements selected by the address lines and storing the parity in the array with the data. Control circuitry is further included for controlling the generation of parity by the parity circuit. The parity generation in this memory system is programmable according to control lines that are connected to the control circuit. The parity circuit may generate the parity output either in the same cycle as the memory access or in the next succeeding cycle of memory access. The output buffer for the parity signal may also be programmable in either a push-pull or a pull-down only configuration.

REFERENCES:
patent: 3992696 (1976-11-01), Fergeson
patent: 4049956 (1977-09-01), Van Veen
patent: 4107650 (1978-08-01), Luke et al.
patent: 4271521 (1981-06-01), Mahmood
patent: 4360917 (1982-11-01), Sindelar et al.

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