Memory system with a socket having socket pins for mounting...

Details Memory system with a socket having socket pins for mounting... Memory system with a socket having socket pins for mounting...

2001-09-28

2004-12-21

Chambliss, Alonzo (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S727000, C257S730000, C257S785000

Reexamination Certificate

active

06833618

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a technique of mounting plural memory modules, specifically to a technique effective for use in a memory system that mounts memory modules on a mother board through sockets and connects each of the memory modules with a memory controller in an equal distance.
The techniques relating to sockets or connectors for memory modules are disclosed, for example, in the Japanese Published Unexamined Patent Publication No. Hei 10 (1998)-3971, Hei 11(1999)-40294, Hei 10(1998)-335546, Hei 8(1996)-314800, Hei 4(1992)-144160 which corresponds to U.S. Patent Publication No. 5,191,404, and so forth.
The Japanese Published Unexamined Patent Publication No.Hei 10(1998)-3971 discloses a technique that when the wirings between the sockets for memory modules are lengthy, the wirings are easily influenced by noises from adjacent signal wirings, and the common signal is directly short-circuited between the sockets by using a short-circuiting plate to shorten the length of the wirings, thereby enhancing the immunity to noises.
The Japanese Published Unexamined Patent Publication No.Hei 11(1999)-40294 discloses a technique that reduces the number of through holes and contacts to be formed on a printed circuit board by using a common bar as a common signal line between the sockets for memory modules, to thereby achieve simplification of the connector structure and reduction of the mounting cost.
The Japanese Published Unexamined Patent Publication No.Hei 10(1998)-335546 discloses a technique that achieves the electrical connection and mechanical support of modules only by a socket member having plural connections in pursuit of a size reduction of the socket that mounts plural modules. The technique achieves the compatibility of the mechanical holding power of the socket member and the overcoat plating facility on the electric contacts of the socket member, by shifting the positions of the contacts of external connection terminals on the front and back sides of the module.
The Japanese Published Unexamined Patent Publication No.Hei 8(1996)-314800 discloses a module for connecting memory modules that possesses plural connection sockets in order to connect the memory modules whose number exceeds the number of the sockets for the memory modules in a computer.
The Japanese Published Unexamined Patent Publication No.Hei 4(1992)-144160 discloses a memory array mechanism that connects a multi-layer board having memory modules mounted thereon as a mutual connection member to the module board so as to face each other with a narrow gap through edge clips.
SUMMARY OF THE INVENTION
In a memory system mounting plural memory modules, the influence given to signal waveforms (deformations of waveforms by reflected waves due to the impedance mismatching) by the length of bus lines on a mother board and the number of the sockets for the memory modules on the bus lines has been an ignorable factor in a synchronous DRAM of which clock frequency exceeds 133 MHz.
Especially, in a bus having multiple slots, the degree of influence to the waveforms that the reflected waves give at the termination greatly differs at the socket near side or at the socket far side, which makes the timing design difficult. And, as the number of the sockets increases, the length of the bus wiring becomes longer, and the wiring capacity increases, which makes it unfit for a high speed operation. Therefore, a shorter bus wiring with a shorter distance between the sockets in addition will achieve a better characteristic.
Accordingly, in this type of memory system, it is essential to design the bus wirings for the memory modules as shorter as possible to comply with a higher speed operation. However, the length of the bus wiring is basically determined by the larger one of the thickness of the socket and that of the module and the number of the socket. As to the thickness of the module, the maximum thickness is settled by JEDEC, and as the result, if the specifications are the same, the widths of the buses will be virtually the same in any products.
Now, the inventor clarified the followings, through the examination of the memory system that mounts the plural memory modules as mentioned above. The technique of the memory system that the inventor examined will be discussed with reference to
FIG. 12
illustrating the structure of the memory system as the premise of the invention,
FIG. 13
illustrating the signal system of the memory system, and
FIG. 14
(
a
),
FIG. 14
(
b
) illustrating the signal waveforms that the memory modules receive.
As shown in
FIG. 12
, in the memory system, for example, a memory controller
101
is directly mounted on a mother board
108
, and three memory modules
102
to
104
each having memory IC are mounted in parallel on the mother board
108
through sockets
105
to
107
each having plural socket pins. By way of the bus wirings on the mother board
108
, each of the memory modules
102
to
104
is connected electrically to the memory controller
101
through the socket pins of each of the sockets
105
to
107
.
In this type of the memory system, from the viewpoint of pursuing a high speed, the influence by the length of the bus wiring becomes ignorable; however, in the parallel arrangement of the memory modules
102
to
104
as shown in
FIG. 12
, there is a limit on the shortening of the bus wiring, from the thickness of the memory modules
102
to
104
or that of the sockets
105
to
107
. Further, it is conceivable that the influences by the reflected waves being different depending on the positions of the sockets
105
to
107
(=bus wiring lengths) will create differences in the waveforms to make the timing design difficult. In other words, the following relation in the nearest memory module
102
and the farthest memory module
104
viewed from the memory controller
101
has been an ignorable factor:
(the difference of the lengths of the bus wirings due to the difference of the positions of the sockets)> thickness of the memory module× (number of the sockets−1)
As shown in
FIG. 13
, in the memory system of the memory modules
102
to
104
of the synchronous DRAM, since the signal from the one memory controller
101
with regard to the signal system common to the modules (address signal: A
0
to A
11
, control signal: /RAS/CAS/WE, data signal: DQ
0
to DQ
63
, data management signal: DQS
0
to DQS
15
, DM
0
to DM
15
) is connected to the bus connecting terminals on the plural boards through a single bus, the lengths of the bus wirings to the memory controller
101
are different with each of the sockets.
In such a signal system common to the modules, with regard to the one-way signals from the memory controller
101
to the memory modules
102
to
104
(address signal, control signal, data management signal) and the clock signal, it is necessary to make the time differences between the clock signal and each of the signals equal to any slots, by regulating the differences of the lengths to the slots.
However, with regard to the data signal that goes and returns, in case of the reverse direction to the clock signal (the readout from the memory modules
102
to
104
), it is impossible to synchronize the data signal with the clock signal. That is, there occur shifts in the timings to the clock signal of the data signals for each slot arriving at the memory controller
101
. Accordingly, a data strobe signal is required as another synchronization signal. When the data signal reads a data being reverse directional to the clock signal, the data strobe signal also advances in the reverse direction to the memory controller
101
from the memory modules
102
to
104
, and serves for transmitting the synchronizing timing of the data signal to the memory controller
101
.
With regard to the signal system independent to each module (clock signal: CK
0
to CK
8
, clock management signal: CKE
0
to CKE
5
, bank selecting signal: CS
0
to CS
5
, power supply signal: Vdd, Vss), one signal pin and one bus connecting terminal are conn

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