Static information storage and retrieval – Addressing
Reexamination Certificate
2000-11-09
2002-04-23
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Addressing
C365S230030
Reexamination Certificate
active
06377500
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention pertains to a memory system with a non-volatile memory. In particular, the present invention relates to a memory system having an address translating function for translating the logical address given to access the non-volatile memory to a physical address.
In recent years, as a memory system for storing a variety of digital information represented by image data or music data, there has been widely known a memory card with a rewritable non-volatile memory in which, even if a power supply is turned OFF, stored information is not erased.
A typical example of such rewritable non-volatile memory includes a NAND type flash memory. A flash memory of such type is managed in blocks. In this memory, information is erased in blocks. The information is erased by an operation for writing data of “1” into all bits contained in blocks. In addition, a logical block address is allocated to one block. Each block consists of a plurality of sectors. Each of these sectors is a minimum unit for read/write operation in a flash memory, and consists of 512 bytes, for example. Each sector has a redundant section other than a data section. A logical block address allocated to a block to which the corresponding sector belongs is registered in a predetermined field of this redundant section.
An address translation table (an address translation mechanism) for translating a logical address to a physical address of the flash memory is required to access the flash memory. A reason required for this address translation is stated below. Namely, this is because, even if a fault block occurs in the flash memory, and is substituted by another empty block, a host system can provide access to a target block with the same logical address irrespective of the presence or absence of such substitution without worrying about the above fault and substitution.
The number of entries in the above address translation table coincides with the number of blocks in a flash memory. For example, in the case where one sector consists of 512 bytes, namely 0.5 KB (kilobytes), and a block consists of 32 sectors, i.e., in the case where a 16 MB (megabyte) flash memory having 16 KB in one block is employed, the number of entries in an address translation table is 16 MB/16 KB=1 K=1,024. The address translation table is generally employed by storing the table in an area (a RAM area) secured on RAM that is a volatile memory. Therefore, in the above example, assuming that one entry is 2 bytes, the RAM area required to store the address translation table is 2 KB.
On the other hand, there has been recently increased the storage capacity of a flash memory with advancement of semiconductor manufacturing technology. For example, there has been introduced a 32 MB flash memory in which the number of blocks is 2,048 and one block consists of 16 KB or a 64 KB flash memory in which the number of blocks is 4,096, and one block consists of 16 KB, and further, a 256 MB flash memory in which the number of blocks is 16,384, and one block consists of 16 KB.
If the storage capacity of the flash memory increases, a RAM area for holding an address translation table must be increased. For example, in the case of a 32 MB flash memory, a 64 MB flash memory, and 256 MB flash memory, a 4 KB RAM area, a 8 KB RAM area, and a 32 KB RAM area are required for the address translation table, respectively. Namely, a RAM area which is twice, four times, and 116 times as large as the 16 MB flash memory is required.
Thus, in a conventional memory card with a rewritable non-volatile memory represented by a flash memory, if the storage capacity of the memory increases, there must be increased an area of a volatile memory represented by a RAM required to hold an address translation table.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in view of the foregoing circumstance. It is an object of the present invention to provide a memory system free of increasing a volatile memory area for an address translation table even if the storage capacity of a non-volatile memory increases.
In order to achieve the aforementioned object, there is provided a memory system comprising: a non-volatile memory storing a plurality of address translation tables to translate into a physical address a logical address given to access the non-volatile memory; a volatile memory having an address translation table area for storing at least one table fewer than the total number of the tables from among the plurality of address translation tables on the non-volatile memory; and means for translating a logical address to a physical address. The address translation tables are associated with their different logical address ranges. When a logical address is given for accessing the non-volatile memory, the translating means translates the logical address into a physical address by utilizing the address translation table corresponding to the logical address on the volatile memory.
In the thus configured memory system, when a logical address is given for accessing a non-volatile memory, address translation for translating the logical address to a physical address is performed by utilizing the address translation table corresponding to the logical address on the volatile memory.
In this manner, in the present invention, at least one table rather than all of the address translation tables on the non-volatile memory is placed on a volatile memory, and the address translation tables on the volatile memory are employed for address translation from a logical address to a physical address. Thus, unlike a case in which all address translation tables are placed on a volatile memory, even if the capacity of the non-volatile memory is increased, it becomes possible to suppress an increase in storage capacity of the volatile memory.
When the address translation table placed on the volatile memory are not the address translation table corresponding to the logical address ranges to which the given logical addresses belong, address translation cannot be performed. The memory system according to the present invention further comprises: means for, when a logical address is given for accessing a non-volatile memory, determining whether the address translation table corresponding to the logical address range to which the logical address belong to exists on the volatile memory; and means for, when it is determined by the determining means that the corresponding address translation table does not exist on the volatile memory, copying the address translation table from a non-volatile memory to the address translation table area on the volatile memory, thereby replacing an original address translation table on the address translation table area.
In the thus configured memory system, when an address translation table required to translate a given logical address into a physical address does not exist in the table area, that is, in the case of table mis-hit the table is copied immediately from the non-volatile memory to the table area, and the original address translation table on the address translation table area is replaced on the address translation table. Therefore, even in the case of table mis-hit, translation from a given logical address to a physical address can be performed speedily. In the meantime, when video data or voice data is read (reproduced) consecutively from a flash memory upon a request from a host system, it is general that a logical address given from the host system is consecutive. Therefore, replacement of the address translation table does not occur frequently due to data reading of such type. It is possible to translate a logical address to a physical address speedily by utilizing the table with respect to the logical addresses that belong to the logical address ranges corresponding to the address translation tables copied to the table area.
For a better understanding of usefulness of the above configuration according to the present invention, there is considered a case in which a configuration is adopted to sequentially generat
Fujimoto Akihisa
Nomura Katsuyuki
Fears Terrell W.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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