Memory system using schottky diodes to reduce load capacitance

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With large area flexible electrodes in press contact with...

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395287, 395309, 395298, 257480, 326 30, G06F 1200, G06F 1202, G06F 926, G06F 932

Patent

active

056995415

ABSTRACT:
A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.

REFERENCES:
patent: 5132564 (1992-07-01), Fletcher et al.
patent: 5323349 (1994-06-01), Hamade et al.
patent: 5448591 (1995-09-01), Goodrich

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