Memory system using faulty bubble memory devices

Details Memory system using faulty bubble memory devices Memory system using faulty bubble memory devices

1979-11-20

1981-09-22

Moffitt, James W.

Static information storage and retrieval

Magnetic bubbles

Plural interacting paths

365200, G11C 1908

Patent

active

042913896

ABSTRACT:
This invention uses a plurality of bubble memory chips in a system for providing simultaneous input and output in a word or byte organized output. Each bubble memory chip has the same number of minor loops as is required for nominal memory size without the requirement for extra or redundant loops. Each bubble memory chip may have a number of faulty minor loops where the bit output is incorrect and cannot be used. However, a requirement for this system is that no two bubble memory chips may have a faulty bit or minor loop at the same major loop address location. An additional bubble memory chip is provided which will contain the correct data bits for locations corresponding to defective major loop addresses in the bubble memory chips making up the byte. A Programmable Read Only Memory (PROM) is provided and connected with a logic network to control the gating of the outputs of the bubble memory chips associated with the memory byte and the extra bubble memory chip to control the gating of the outputs. Thus, as contents of the various bubble memory chips are addressed, the PROM controls the gating of the bits forming the output byte or word so that the output byte or word is comprised of only correct bits.

REFERENCES:
patent: 4073012 (1978-02-01), Ohnigian et al.
patent: 4233669 (1980-11-01), Furukawa et al.
IBM Technical Disclosure Bulletin-vol. 18, No. 9, Feb. 1976, pp. 3079-3081.
IBM Technical Disclosure Bulletin-vol. 19, No. 12, May 1977, pp. 4758-4761.

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