Memory system, method for verifying data stored in a memory syst

Details Memory system, method for verifying data stored in a memory syst Memory system, method for verifying data stored in a memory syst

1999-08-12

2000-08-22

Fears, Terrell W.

Static information storage and retrieval

Addressing

36518901, G11C 1300, G11C 1606

Patent

active

061082635

ABSTRACT:
A memory system (20) comprising a memory array (22) having a plurality of memory cells (42) arranged in rows and columns. Each memory cell (42) has a control terminal. A voltage controller (26) provides to the control terminal of a memory cell a first verify voltage signal (Vabse) during a first verify cycle or a second verify voltage signal (Vabsp) during a second verify cycle. The first verify voltage signal (Vabse) having a predetermined voltage level that corresponds substantially to a threshold voltage level of a memory cell in the array in a first state and the second verify voltage signal (Vabsp) having a predetermined voltage level that corresponds substantially to a threshold voltage level of a memory cell in the array in a second state.

REFERENCES:
patent: 5313429 (1994-05-01), Chevallier et al.

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