Memory system having self timed daisy chained memory chips

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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Details

C365S051000, C711S005000, C711S154000, C711S167000

Reexamination Certificate

active

07545664

ABSTRACT:
A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on a memory chip is determined by a self time block on the memory chip.

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