Memory system having multi-terminated multi-drop bus

Details Memory system having multi-terminated multi-drop bus Memory system having multi-terminated multi-drop bus

2007-09-25

2007-09-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S198000, C365S051000

Reexamination Certificate

active

11142873

ABSTRACT:
Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value. The first load, the second load, and a first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof.

REFERENCES:
patent: 6744332 (2004-06-01), Bois et al.
patent: 6754132 (2004-06-01), Kyung
patent: 6930904 (2005-08-01), Wu

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