Memory system having memory controller for controlling...

Details Memory system having memory controller for controlling... Memory system having memory controller for controlling...

2002-01-29

2003-11-18

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230010

Reexamination Certificate

active

06650593

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory system having a plurality of types of memory chips and a memory controller for controlling these memory chips.
2. Description of the Related Art
With the progression of semiconductor manufacturing technology and semiconductor design technology, it has become possible to implement one whole system on a single semiconductor chip. A semiconductor that operates as a single system is generally referred to as a system LSI. A system LSI contains, for example, an MPU core for controlling the entire system, peripheral cores (IP cores) having a predetermined function, and a memory core. The memory core stores programs necessary for the operation of the system, data for the system to handle, and so on.
Recently, there have been developed portable apparatuses that handle large amounts of data such as moving images. When these portable apparatuses use memory capacities beyond those of the memory cores mounted on their system LSIs, it is usual to constitute the systems with semiconductor memories (memory chips) externally attached to the system LSIs. The reason for this is that if high capacity memory cores are incorporated into the system LSIs, the system LSIs increase in chip size and might drop in yield.
Furthermore, logic products such as an MPU and memory products such as a DRAM are optimized in design for respective features, and manufactured under respective optimum conditions. Accordingly, designing and manufacturing the memory chips aside from the system LSIs (logic chips) can improve system performance.
FIG. 1
shows an example of the system (memory system) in which a plurality of types of memory chips are externally attached to a system LSI. Here, a memory system refers to a set of functions of a system constituting the above-mentioned portable apparatus or the like that are necessary for memory operation.
The memory system comprises a system LSI
2
and a plurality of types of memory chips
3
a
,
3
b
, and
3
c
to be mounted on a printed-circuit board
1
. The system LSI
2
has an MPU
4
for controlling the entire system, peripheral cores (IP)
5
a
and
5
b
having a predetermined function, and memory controllers
6
a
,
6
b
, and
6
c
corresponding to the memory chips
3
a
,
3
b
, and
3
c
, respectively. The memory chips
3
a
,
3
b
, and
3
c
are respectively connected to the memory controllers
6
a
,
6
b
, and
6
c
through buses
7
a
,
7
b
, and
7
c
which are laid on the printed-circuit board
1
.
Conventionally, in the case of constructing the memory system from the system LSI
2
and the plurality of types of memory chips
3
a
,
3
b
, and
3
c
, it has been required, as described above, that the memory chips
3
a
,
3
b
, and
3
c
be individually provided with the memory controllers
6
a
,
6
b
, and
6
c
. For example, SDRAMs and flash memories have different command systems and operation timing for performing write operations and read operations. Therefore, SDRAMs and flash memories have necessitated their respective memory controllers when externally attached to a system LSI. As a result, there has been a problem that the system LSI
2
grows in chip size and increases in chip cost.
Since the terminals of the memory chips
3
a
,
3
b
, and
3
c
are connected to the terminals of the system LSI
2
through the buses
7
a
,
7
b
, and
7
c
, respectively, the number of terminals of the system LSI
2
becomes enormous. Consequently, the system LSI
2
might be greater in chip size depending on the number of terminals. In worst cases, it has been necessary to develop a new package for the number of terminals of the system LSI
2
.
Since the plurality of memory controllers
6
a
,
6
b
, and
6
c
are mounted on the system LSI
2
, the system LSI
2
has been greater in circuit scale, requiring an enormous amount of time for design verification.
The formation of the buses
7
a
,
7
b
, and
7
c
necessitates large numbers of wires on the printed-circuit board
1
. Consequently, there has been a problem that the wiring layers of the printed-circuit board
1
grows in number, increasing the design cost and manufacturing cost of the printed-circuit board
1
.
Clock synchronous SDRAMs have been developed to improve the data transmission rates of DRAMs. For other clock asynchronous semiconductor memories (including nonvolatile memories), products of clock synchronous type are also likely to be developed.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the costs of a memory system that has a plurality of types of memory chips and a memory controller for controlling these memory chips.
Another object of the present invention is to provide a common interface in a memory system comprising a system LSI with a plurality of types of memory chips externally attached, the common interface connecting the memory chips and the system LSI for controlling the memory chips.
Still another object of the present invention is to attach clock synchronous nonvolatile memories externally to a system LSI with facility and lower costs.
According to one of the aspects of the memory system of the present invention, the memory system comprises: a plurality of types of memory chips operating in synchronization with a clock signal; a controller for issuing access requests to the memory chips; a memory controller for controlling the memory chips; and a common bus for connecting the memory chips and the memory controller to transmit memory input signals and memory output signals. The memory chips include, for example, a volatile memory such as a synchronous DRAM and a nonvolatile memory such as a clock synchronous NAND type flash memory.
The memory controller converts, according to operation specifications of the memory chips to operate, controller output signals which the controller outputs to the memory controller when operating memory chips, into the memory input signals receivable to the memory chips. The memory chips receive the memory input signals and perform a read operation, a write operation, or the like. Among the controller output signals and the memory input signals are address signals, command signals, and write data signals.
The memory chips output read data signals obtained through their read operations to the common bus as the memory output signals. The memory controller receives the memory output signals through the common bus, and converts the received signals into read data signals (controller input signals) receivable to the controller. Then, the controller receives the controller input signals, thereby completing the read operations of the memory system.
As described above, the memory controller converts controller output signals into memory input signals receivable to the individual memory chips. This allows the single memory controller to access the plurality of types of memory chips. As a result, the plurality of memory chips can be connected to the memory controller through the common bus, which can minimize a number of signal lines. In addition, the memory controller can be reduced in circuit scale. The memory controller need not be designed anew upon each development of memory chips as heretofore.
According to another aspect of the memory system of the present invention, the memory output signals and the memory input signals received respectively by the memory controller and the memory chips through the common bus have the same input timing specification irrespective of which of the memory chips is to operate. Similarly, the memory input signals and the memory output signals output respectively from the memory controller and the memory chips through the common bus have the same output timing specification irrespective of which of the memory chips is to operate. On this account, the memory controller can reliably access the plurality of types of memory chips having different operation specifications by simply adjusting the output order of the memory input signals and the acceptance order of the memory output signals according to the command specif

Affiliated with

Also associated with

Rating

Memory system having memory controller for controlling... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory system having memory controller for controlling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory system having memory controller for controlling... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3160675