Memory system having defective address identification and replac

Details Memory system having defective address identification and replac Memory system having defective address identification and replac

1996-02-08

1998-05-26

Decady, Albert

Excavating

371 102, G06F 1100

Patent

active

057580561

ABSTRACT:
The present invention is embodied in a memory system which restores full functionality to a dynamic random access main memory having at least one defective bit. In a preferred embodiment of the invention, the memory system is integrated on an industry standard memory module which is plugged into a host computer system. The memory module incorporates a block of DRAM main memory, an SRAM replacement memory, a non-volatile memory which stores a map of defective memory locations within the main memory, and a process control module (PCM) operable in multiple modes, which manages a defective address identification and replacement process. The PCM, which contains high-speed registers, in addition to decoding and control logic, is implemented as a high-speed application-specific integrated circuit (ASIC). The PCM, which is coupled to both the host system memory address and data buses, recognizes addresses of defective memory locations within the main memory block and, in response to such recognition, suppresses output from the main memory block and provides a replacement address within the high-speed SRAM memory. The data stored at the replacement address is output to the system data bus. The process operates with sufficient speed to ensure that there is no degradation in main memory access time. The non-volatile memory can be updated by the host system to correct newly discovered defects in the main memory without removing the memory module from the system.

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