Memory system for reliably writing addresses with reduced power

Details Memory system for reliably writing addresses with reduced power Memory system for reliably writing addresses with reduced power

1990-10-22

1992-07-14

Fears, Terrell W.

Static information storage and retrieval

Powering

Conservation of power

365 49, 365226, G11C 1140

Patent

active

051309475

ABSTRACT:
A memory system for translating addresses has an active pull-up transistor per CAM entry for guaranteeing that a valid CAM entry is loaded in a CAM array prior to addressing a RAM entry in A RAM array. The CAM has a load device connected to each entry for dynamically activating each CAM entry during an address translation. The RAM array has a plurality of RAM entries wherein each RAM entry is connected to a predetermined CAM entry by a Match-Line. A predetermined one of a plurality of driver transisors is connected to each active Match-Line for selectively charging each Match-Line to a predetermined active state during an address write operation, thereby reducing power consumed by non-selected CAM entries. Only one Match-line remains active in response to a "Hit" condition. Feedback between each Match-Line to a validity bit cell in each entry of the CAM is used to set each validity bit only after a successful write of a CAM entry.

REFERENCES:
patent: 4646271 (1987-02-01), Uchiyama et al.

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