Patent
1994-11-14
1996-12-17
Lane, Jack A.
39542107, 395496, G06F 1206
Patent
active
055862829
ABSTRACT:
A memory access system employs a pipe-line process in which access can be carried out for a microprocessor using one cycle of two clocks and for a microprocessor using one cycle of one clock. Access speed of a main memory can be considerably improved ensuring applicability in general use. A transition request signal to a pipe-line is received, a control signal that continues as long as the cycle number corresponding to at least the address first-out number of the pipe-line immediately after the start of the pipe-line operation is produced. Concurrently, a data complete signal indicating the completion of data access for a bank is produced during the time that either of the above two signals is also generating an address latch signal synchronized to a clock signal and routed to respective banks, for executing high speed data access.
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Iino Hideyuki
Takahashi Hiromasa
Fujitsu Limited
Lane Jack A.
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