Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2001-04-30
2003-09-30
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S077000, C257S133000, C257S296000, C257S107000, C257S155000, C257S146000, C438S105000, C438S931000, C438S135000
Reexamination Certificate
active
06627924
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, the invention relates to a memory system fabricated over a silicon carbide (SiC) substrate for operating at high temperatures. More specifically, the invention relates to a memory system having a plurality of Thyristor-based Random Access Memory (T-RAM) memory cells capable of operating at high temperatures and method for fabricating the memory system. Each T-RAM memory cell has dual vertical devices and a planar cell structure.
BACKGROUND OF THE INVENTION
A low-power, high-speed and high-density negative differential resistance (NDR) based (NDR-based) SRAM cell which can provide DRAM-like densities at SRAM-like speeds has been proposed by Farid Nemati and James D. Plummer in “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device,” 1998 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pages 66-67, 1998.
The memory device structure is shown by FIG.
1
and is designated by reference numeral
10
; the memory device structure is called a Thyristor-based Random Access Memory (T-RAM) memory cell. The T-RAM device or memory cell
10
consists of a thin vertical pnpn thyristor
12
with a surrounding nMOS gate
14
as the bistable element and a planar nMOSFET as the access transistor
16
. The circuit schematic of the T-RAM memory cell
10
is shown by FIG.
2
.
To access the T-RAM memory cell
10
, two wordlines are necessary. The first wordline WL
1
is used to control an access gate of the transfer nMOSFET device
16
, while the second wordline WL
2
is the surrounding nMOS gate
14
which is used to control the switch of the vertical pnpn thyristor
12
. The thyristor
12
is connected to a reference voltage Vref. The second wordline WL
2
improves the switching speed of the thyristor
12
from 40 ns to 4 ns with a switching voltage. A bitline BL connects the T-RAM memory cell
10
to a sense amplifier for reading and writing data from and to the T-RAM memory cell
10
. The T-RAM memory cell
10
exhibits a very low standby current in the range of 10 pA.
When writing a “high”, the bitline BL is set at low, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a forward biased pn diode. After a write operation, both gates are shut off, and a “high” state is stored in the thyristor
12
. In a read operation, only the first wordline WL
1
is activated, a large “on” current will read on the bitline BL through the access gate. When writing a “low”, the bitline BL is set at “high” state, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a reverse biased diode. After the write operation, both gates are shut off, and a “low” state is stored in the thyristor
12
. Similarly, in a consequence read, a very low current will be detected on the bitline BL. Further details of the operation of the T-RAM memory cell
10
and its gate-assisted switching are described in Nemati et al.; the contents of which are incorporated herein by reference.
A T-RAM array having a plurality of T-RAM memory cells
10
has demonstrated a density equivalent to that of DRAM arrays and a speed equivalent to that of SRAM arrays. Hence, the T-RAM array provides advantages afforded by both SRAM and DRAM arrays. These advantages make T-RAM an attractive choice for future generations of high speed, low-voltage, and high-density memories and ASICs.
However, there are several drawbacks of the T-RAM memory cell
10
. First, there is the requirement of forming the thyristor
12
having a vertical pillar on a substrate during a fabrication process. Difficulties arise in controlling the dimensions of the vertical pillar and reproducing these dimensions for each T-RAM memory cell
10
in the T-RAM array. Second, due to the existence of a vertical thyristor
12
in each T-RAM memory cell
10
, each T-RAM memory cell
10
is not planar and therefore difficult to scale.
Third, it is difficult to control the dimension while forming the surrounding gate around the base of each vertical thyristor
12
. Fourth, each T-RAM memory cell
10
is fabricated prior to or after fabricating any other devices, such as p-MOS and n-MOS support devices (i.e., sense amplifiers, wordline drivers, column and row decoders, etc.), which results in extra fabrication steps, thereby increasing thermal budget and manufacturing cost. Further still, due to these drawbacks, the resulting T-RAM memory cell
10
cannot be smaller than 8F
2
and the cost of fabricating a T-RAM array is high.
An additional drawback of the prior art T-RAM memory cell
10
, and of prior art memory cells as well, is that it cannot be properly operated at an elevated temperature, e.g., at temperatures greater than 200 degrees Celsius. This is because the prior art memory cells are fabricated in silicon substrate which cannot sustain relatively high operating temperatures.
Silicon carbide (SiC) is a wide bandgap semiconductor which has many performance advantages over silicon. For example, SiC has a high saturation electron velocity, a high junction breakdown voltage, a high thermal conductivity and a broad operating temperature range (up to 1100 degrees Celsius). The thermal conductivity and breakdown voltage of SiC are an order of magnitude higher than conventional semiconductor materials, such as Si, GaAs and InP. The maximum operating temperature range of SiC is at least twice of that of the conventional semiconductors.
SiC fabricated devices are attractive for applications involving high temperatures, such as avionics. Additionally, the crystal lattice structure of SiC is tolerant to radiation. Therefore, devices fabricated using SiC are less susceptible to radiation damage than devices fabricated from conventional semiconductor materials.
Accordingly, a need exists for a memory system having a plurality of T-RAM cells arranged in an array and fabricated over a SiC substrate, in order for the array to be operational at high temperatures and immune from high radiation. A need also exists for a method of fabricating the T-RAM array over the SiC substrate.
SUMMARY
An aspect of the present invention is to provide a memory system having a plurality of T-RAM cells arranged in an array and fabricated over a SiC substrate, in order for the array to be operational at high temperatures and immune from high radiation.
Another aspect of the present invention is to provide a T-RAM array having a plurality of T-RAM cells fabricated over a SiC substrate, where each of the plurality of T-RAM cells has a planar cell structure and dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate.
Also, another aspect of the present invention is to provide a memory system having a plurality of T-RAM cells arranged in an array and fabricated over a SiC substrate, wherein each of the plurality of T-RAM cells has a planar cell structure and dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate.
Further, another aspect of the present invention is to provide a method for fabricating a high-density, high-yield and low-cost T-RAM array having a plurality of T-RAM cells and a planar cell structure over a SiC substrate. Each of the plurality of T-RAM cells has a planar cell structure and dual vertical devices, i.e., a vertical thyristor and a vertical transfer gate.
Further still, another aspect of the present invention is to provide a method for fabricating a T-RAM array on a SiC substrate for operating the T-RAM array at high temperatures and in radiation-prone environments.
Finally, another aspect of the present invention is to provide a method for fabricating a T-RAM array where the method improves performance and yield, and reduces cost and thermal budget.
Accordingly, in an embodiment of the present invention, a T-RAM array fabricated over a SiC substrate is presented. The T-RAM array has a planar cell structure and a plurality of T-RAM cells where each T-RAM cell has dual vertical devices. That is, each T-RAM cell has a vertical thyristor
Hsu Louis L.
Wang Li-Kong
Crane Sara
Dilworth & Barrese LLP
IBM Corporation
Im Junghwa
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