Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2003-01-14
2004-06-01
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189011, C711S004000, C711S117000, C711S118000
Reexamination Certificate
active
06744692
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique of buffering access data in a memory system for performing access control between an external interface and a nonvolatile memory in response to an access request from the outside and, for example, to a technique effectively applied to a flash memory card.
A flash memory card has a flash memory and a controller. Since the operation speed, particularly, writing or rewriting operation speed of the flash memory is lower than operation speed of a host connected to the flash memory card, the controller has a buffer memory in order to absorb the difference between the operation speeds. In response to a write request from the outside, the controller controls to input write data from the outside to the buffer memory and write the input data into the flash memory. In response to a read request from the outside, the controller temporarily stores data read out from the flash memory into the buffer memory and outputs the stored data to the outside. As a conventional buffer memory, an SRAM (Static Random Access Memory) of a relatively small capacity, a static latch, or the like is often employed.
SUMMARY OF THE INVENTION
In the case of employing an SRAM of a small capacity, however, until writing of data input from the outside to the buffer memory into the flash memory is completed, data transfer from the host to the memory card has to be waited. Until read data stored in the buffer memory from the flash memory is output to the outside, a new reading operation of the flash memory has to be waited. Particularly, in the case where writing of data into the flash memory fails, for example, when the data has to be written again to a replacing sector due to a failure in a sector to which the writing operation is performed first, the next write data from the host cannot be received by the buffer memory. Consequently, due to a problem between the flash memory and the controller, data transfer between the host and the controller has to be waited. It increases burden on the host and processing time, and a problem such that the data processing efficiency deteriorates occurs.
In a process of examining the problems, the inventor herein has recognized the existence of patent applications, although not well known, filed by the applicant herein. The patent application Nos. are 2001-174978, 2001-177924, 2001-213639, and 2001-213640. The applications provide a technique using a flash memory as a nonvolatile memory for backing up information stored in an SDRAM as a volatile memory. The SDRAM is not evaluated as a buffer memory.
An object of the present invention is to provide a memory system contributing improvement in efficiency of a data process accompanying a memory access.
Another object of the invention is to provide a memory system for performing an access control between an external interface and a nonvolatile memory in response to an access request from the outside, which can contribute to reduction in waiting time of a host in data transfer to/from the host, reduction in process load, and reduction in process time.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the accompanying drawings.
Representative ones of inventions disclosed in the specification will be briefly described as follows.
[1] A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory and transfer from the buffer memory to the controller in the third data transfer in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
With the above configuration, in response to a write access request from the outside, the controller stores write data to the buffer memory and outputs the write data stored in the buffer memory in a time sharing manner, in parallel with the write data storing process, can transfer write data to the nonvolatile memory by the second data transfer and, in parallel with the write data outputting process, input the following write data from the external apparatus by the first data transfer. In response to a read access request from the outside, the controller stores read data to the buffer memory and outputs the read data stored in the buffer memory in a time sharing manner, in parallel with the read data storing process, can transfer the read data to the external apparatus by the first data transfer and, in parallel with the read data outputting process, input the following read data from the nonvolatile memory by the second data transfer.
By the buffering function of the buffer memory, long waiting time is unnecessary for the timing of supplying a plurality of write data pieces by an external apparatus such as a host, and long waiting time is unnecessary for the timing of obtaining a plurality of read data pieces by the host. Therefore, the invention can contribute to reduction in waiting time of the host in the data transfer between the host and a controller, reduction in a process load, and reduction in processing time. Thus, the invention can contribute to improvement in the efficiency of a data process accompanying a memory access.
As a desired mode of the invention, in order to maximally display the buffering function, operation speed of the third data transfer is about twice as high as data transfer speed of the first data transfer. In theory, the waiting time of the host becomes zero.
As a desired mode of the invention, the buffer memory is a single-port clock-synchronous volatile memory and operates in an FIFO manner. Higher speed of the buffer memory and easy access control can be realized. The nonvolatile memory is, for example, a flash memory.
As a mode of realizing buffering between the first transfer and the third transfer and buffering between the second transfer and the third transfer, preferably, the controller has a dual-port data buffer disposed between the external apparatus and the buffer memory and a dual-port data buffer disposed between the buffer memory and the nonvolatile memory. Control for paralleling the first data transfer and the third data transfer and paralleling the second data transfer and the third data transfer is further facilitated.
[2] A memory system according to another aspect of the invention has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller has: a first data transfer control unit connected to an external apparatus; a second data transfer control unit connected to the nonvolatile memory; and a transfer arbitrator which is connected to the buffer memory and controls data transfer to/from the buffer memory in response to a transfer request from the first data transfer control unit and a transfer request from the second data transfer control unit. The first data transfer control unit is connected to the external apparatus and the transfer arbitrator via a dual-port data buffer and outputs a transfer request to the transfer arbitrator. The second data transfer control unit is connected to the nonvolatile memory and the transfer arbitrator via a dual-port data buffer and outputs a transfer request to the transfer arbitrator. The transfer arbitrator controls transfer of write data to the buffer memory and transfer of read data from the buffer memory in a time sharing manner in response to a transfer request from the first data transfer control unit and a transfer request from the second data transfer control unit.
With the above configuration, the data transfer between the external apparatus and the controller is buffered by the data buffer in the first data transfer control uni
Goto Hiroyuki
Hara Fumio
Nakamura Yasuhiro
Shibuya Hirofumi
Shiota Shigemasa
Miles & Stockbridge P.C.
Nguyen Van-Thu
Renesas Technology Corp.
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