Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-25
2002-07-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185120, C365S185230
Reexamination Certificate
active
06426895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory system and its programming method using a non-volatile memory in which writing is carried out by every page unit.
2. Description of the Related Art
FIG. 21
is a block diagram illustrating a configuration example of a conventional memory system using an NAND-type flash memory array.
This memory system
1
has a control portion
2
and a memory portion
3
, as a main configuration component.
The control portion
2
has a page buffer
21
, an error correction circuit (ECC)
22
, a write register (WR.Reg)
23
, a read register (RD.Reg.)
24
, a command register (Command Reg.)
25
, a configuration ROM (Config ROM)
26
, an external interface
27
for performing serial (S)/parallel (P) conversion of write data from the external portion and for performing parallel (P)/serial (S) conversion of read data from the memory portion
3
to output to the external portion, ana a memory interface
28
.
Further, the memory portion
3
has a memory-cell array
32
in which an NAND-type flash memory array is arranged, a register
31
and a control circuit that is not illustrated.
Note, the data register
31
is constituted by a command register, a data register and other register(s).
The programming (write) operation of this memory system will be explained.
Conventionally, in a non-volatile memory, such as an NAND-type flash memory, since the programming (write) speed of a memory itself is slow, for instance, as illustrated in
FIG. 22A
, the page buffer
21
stores therein data once.
Next, as illustrated in
FIG. 22B
, data is transferred by means of internal transfer from the page buffer
21
to the register
31
of the memory portion
3
.
Finally, as illustrated in
FIG. 22C
, the process is made to execute collectively the programming of data for one page (for instance, data for 512 bytes connected 1 word line), namely, the programming of the memory-cell array for one-page data from the register
31
is executed.
FIG. 23
is a schematic view illustrating program timing of the NAND-type flash memory.
In the programming of the NAND-type flash memory, as illustrated in
FIG. 23
, a command (CMD) is input to the register
31
in the period t
1
, the input is made to execute an address (ADR) that is input to the register
31
in the subsequent period t
2
, and the data for one page of 512 bytes is input to the register
31
in the further subsequent period t
3
.
Then, writing is made to execute collectively data for one page of 512 bytes input in the period t
4
in accordance with the input command and address.
As described above, in the conventional memory system, since a NAND-type flash memory that is capable of carrying out collectively writing for each page is employed and writing is made to execute collectively one page for data to be programmed by each page, the total programming time required for input of command, address and data, further actual programming is long (maximum writing time of one page is up to about 1500 &mgr;s), and thus it may be difficult to apply to such the NAND-type flash memory to a memory system, such as a memory card, which requires high-speed operation.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory system and a programming method capable of shortening the programming time for each page and applicable in a variety of systems.
In order to achieve the above-mentioned object, according to a first aspect of the present invention, there is provided a memory system in which a program is completed with a page as a unit comprising: an intermediate circuit successively holding program data that form the page in a division unit where the program data is divided into a plurality of division units; a memory-cell array in which a plurality of memory cells, each including at least one memory transistor having a control gate controlling a charge accumulating means and a charge quantity accumulated in the charge accumulating means, in which at least one selection transistor having a shared channel formation region and the memory transistor are arranged, and in which the plurality of memory cells arranged in the direction of a word line are connected in a cascade connection; word lines to which gates of the selection transistors of each memory cell cascade-connected in the direction of the word line are commonly connected; and a control circuit successively reading the divided unit data held in the intermediate circuit when programming, electrically dividing the memory-cell array in every interval of a plurality of the memory cells in response to the division unit in the direction of the word line by driving the control gate of the memory transistor, and writing the division unit data to the memory-cell array by parallel applying programming pulses to the control gates of the memory transistors in a predetermined bit unit.
In accordance with a second aspect of the present invention, there is provided a memory system in which a program is completed with a page as a unit comprising: a plurality of divided circuits each having an intermediate circuit successively holding programming data that form a page(s) in a division unit where the program data is divided into a plurality of division units, a memory-cell array in which a plurality of memory cells, including at least one memory transistor having a control gate controlling a charge accumulating means and a charge quantity accumulated in the charge accumulating means, in which at least one selection transistor having a shared channel formation region and the memory transistor are arranged, and in which the plurality of memory cells arranged in the direction of a word line are connected in cascade connection; word lines to which a gate of the selection transistor of each memory cell cascade-connected in the direction of the word line are connected commonly; and a control circuit constituting pages in such a way as to range over a plurality of divided circuits, successively reading divided unit data held in the intermediate circuit when programming, electrically dividing the memory-cell array at intervals of a plurality of the memory cells corresponding to the divided unit in the direction of the word line by driving the control gate of the memory transistor of each divided circuit, and writing the divided unit data to the memory-cell array by applying programming pulses in parallel to the control gate of the memory transistor in a predetermined bit unit with ranging over the plurality of divided circuits.
The control circuit may carry out an application of the programming pulse application in parallel, and it continuously carries out the verification in all the same bit unit.
The charge accumulating means of the memory cell may include an insulating film that includes a nitride film.
The memory cell may include a first memory transistor, a second memory transistor and a selection transistor formed to have a common channel formation region between the first memory transistor and second memory transistor, the charge accumulating means of both the memory transistor and second memory transistor is included in the insulating film that includes the nitride film, and the first memory transistor of one memory cell and the second memory transistor of the memory cell adjacent to the one memory cell commonly have an insulating film as the control gate and the charge accumulating means.
In accordance with a third aspect of the present invention, there is provided a programming method for a memory system having a memory-cell array in which a plurality of memory cells, each including at least one memory transistor having a control gate controlling a charge accumulating means in which a charge quantity accumulated in the charge accumulating means, and at least one selection transistor having a shared channel formation region and the memory transistor are arranged, in which a plurality of memory cells arranged in the direction of a word line are connected in a cascade connection, and in which programming is completed wi
Hashiguchi Akihiko
Kosaka Hideo
Okaue Takumi
Auduong Gene N.
Kananen, Esq. Ronald P.
Nelms David
Rader & Fishman & Grauer, PLLC
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