Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-09-11
2007-09-11
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233500, C365S193000, C365S194000, C365S191000
Reexamination Certificate
active
11352131
ABSTRACT:
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.
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Johnson Brian
Keeth Brent
Lee Seong-hoon
Lin Feng
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Viet Q.
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