Boots – shoes – and leggings
Patent
1990-02-09
1992-10-13
Clark, David L.
Boots, shoes, and leggings
364DIG1, 3642469, 380 4, G06F 1214
Patent
active
051558297
ABSTRACT:
A secure read only memory in which an external address of (n-m) bits is applied to an address controller which converts the external address into an n bit internal address which is applied to a read only memory to obtain data stored in the read only memory at the address locations. The address controller includes detector circuits for detecting improper accesses to the memory. In response to an improper access to the memory, the memory controller will produce an improper access signal which improper access signal is used to terminate operation of the system or to modify the address so that the data produced in response to the external address has essentially no direct reproducable relationship to the actual address of the memory location of the random access memory where the data is stored.
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Berkebile HE et al., "High Speed Cache in Front of Low Speed Storage", IBM Technical Disclosure Bulletin, vol. 25, No. 8, pp. 4287-4288.
Clark David L.
Weiss Harry M.
Weiss Harry M.
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