Memory system and method

Details Memory system and method Memory system and method

1995-12-01

1996-11-19

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365200, 371 401, 371 404, G11C 700, G11C 800, G11C 2900

Patent

active

055770045

ABSTRACT:
A memory system wherein a plurality of memory banks is provided, each having a plurality of addressable memory units. A driver is coupled to a set of address terminals of a corresponding one of the memory units in each one of the memory banks. Each bit of data is fed to a data terminal of a corresponding one of the memory units in each one of the memory banks. An error detection and correction (EDAC) unit is fed by the data passing to, or from, the memory system. With such an arrangement, a failure of any one of the drivers results in an error in only one bit of the data stored in the incorrectly addressed location, and such single bit error is corrected by the EDAC unit upon its retrieval from the memory system.

REFERENCES:
patent: 4797850 (1989-01-01), Amitai
patent: 5313425 (1994-05-01), Lee et al.
patent: 5379415 (1995-01-01), Papenberg et al.

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