Memory system and cache memory system

Details Memory system and cache memory system Memory system and cache memory system

1994-08-04

1996-03-19

Nguyen, Viet Q.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518907, 36518908, 36518905, 36523003, 36523006, 365231, G11C 11413, G11C 1504

Patent

active

055008143

ABSTRACT:
A memory system, wherein the respective byte memories 1 to 4 is configured so that data of word unit which are the targets of the parity calculation done by the parity calculation circuits 5 to 8 occupy respectively the same bit positions as those of the 4-word data of word unit, is provided with multiplexers 41 to 44 for connecting selectively to the data bus 29 the bit positions of the data of word unit selected by the word select control circuit 23 in such byte memories 1 to 4. The memory system is capable of improving the flexibility of the memory configuration by being eased of the limitation of the arrangement of bits which are the targets of parity calculation, and reducing the occupied areas of the write/read circuit on a chip as well as the electric power consumption.

REFERENCES:
patent: 4641305 (1987-02-01), Joyce et al.

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