Memory system

Details Memory system Memory system

2001-02-08

2002-01-01

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S239000

Reexamination Certificate

active

06335903

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory system, and more particularly, to a memory system where a DRAM or synchronous DRAM is used as a storage device.
2. Description of Related Art
Conventionally, as a main storage of a supercomputer or a large-scale computer which must meet a requirement for high performance, an SRAM capable of high-speed operation is used. However, the SRAM is very expensive in comparison with other storage devices, and a huge mounting area is required in the integrated circuit. Accordingly, in accordance with heated cutthroat price competition and downsizing in recent years, it is desired to construct the main storage of supercomputer and the like with a cheaper and higher density DRAM. Then, in personal computers, use of DRAM or synchronous DRAM which is now becoming the main stream storage can be considered.
Addresses of DRAM and synchronous DRAM are divided into row addresses and column addresses. Data is read from or written into an arbitrary memory cell by first designating a row address then designating a column address after a predetermined waiting period. Further, in a case where designation of row address and column address are made with respect to a DRAM or synchronous DRAM, these designated addresses are transmitted via the same address line to the DRAM or synchronous DRAM. At this time, to discriminate the row address from the column address, a row address strobe signal is turned ON upon designation of row address, and a column address strobe signal is turned ON upon designation of column address.
Further, in the DRAM, when an initial row address has been designated, the contents of all the corresponding memory cells are stored into a temporary buffer. The buffer is released by a precharge command. Further, the precharge command may be issued at the same time of issuance of column address or may be issued independently. That is, for memory access requests having the same row address, column addresses can be continuously designated. In the supercomputer for which high-speed access is required and the like, this function must be fully utilized.
Japanese Published Patent Application No. Hei 07-210456 discloses a technique to improve utilization efficiency in a DRAM high-speed access mode. A row address to be currently issued to the DRAM is held in a first register, and a row address previously issued to the DRAM is held in a second register. Then a change of row address is detected by comparing the contents of the registers. If the high-speed access mode is not set although the row address has not changed, the ON period of row address strobe signal is increased. On the other hand, if the high-speed access mode is set although the row address has changed, the ON period of the row address strobe signal is reduced. As a result, in a case where memory access is repeated with respect to the same row address, the high-speed access mode is set for a long period, while in a case where the row address frequently changes, the high-speed access mode ends in a short period.
In the above-described conventional art, in a case where high-speed memory access is to be realized, a problem occurs when the comparison between row addresses must be quickly performed, since in application of this technique, the row address comparison must be completed before the issuance of column address. However, the speed of row address comparison tends to be slower by the increase in row address bits in accordance with recent mega-capacity storages.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to realize high-speed memory access by performing row address comparison at a high speed.
According to one aspect of the present invention, a memory system comprises means for extracting a row address part from an access address accompanying a memory access request, a buffer for storing the extracted row address, means for comparing the extracted row address with the row address stored in the buffer, a pointer register for storing a pointer to the buffer holding the row address, and a pointer buffer having a function of comparing stored pointers.
Further, the system comprises means for avoiding registration of the same row address within the buffer for storing row addresses, a control circuit which detects correspondence between row addresses between access requests from the result of comparison between stored pointers, and a control circuit which continuously issues column addresses in plural requests with row addresses corresponding to each other, to a DRAM or synchronous DRAM.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same name or similar parts throughout the figures thereof.


REFERENCES:
patent: 4680701 (1987-07-01), Cochran
patent: 5410513 (1995-04-01), Masuda et al.
patent: 5801981 (1998-09-01), Iwakiri
patent: 6000016 (1999-12-01), Curtis et al.
patent: 7-210456 (1995-08-01), None

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