Memory subsystem having a static row memory and a dynamic RAM

Details Memory subsystem having a static row memory and a dynamic RAM Memory subsystem having a static row memory and a dynamic RAM

1993-07-26

1995-05-30

Shin, Christopher B.

Boots, shoes, and leggings

395275, 3642436, 36424341, 364DIG1, 36518901, G06F 1200

Patent

active

054210003

ABSTRACT:
A computer memory subsystem is comprised of one or more Dynamic Random Access Memory (DRAM) arrays with on-chip sense latches for storing data outputted from the DRAM, an on-chip Static Random Access Memory (SRAM) functioning as a Distributed Cache and an on-chip multiplexor. A first data bus interconnects the sense latches, the SRAM and the multiplexor. A second data bus interconnects the multiplexor and the SRAM. A memory controller generates signals which cause information to be extracted from the DRAM while the contents of the SRAM is unchanged or vice versa.

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