Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Bulk effect switching in amorphous material
Reexamination Certificate
2005-09-06
2005-09-06
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Bulk effect device
Bulk effect switching in amorphous material
C257S530000, C257S529000, C257S003000, C365S163000, C365S174000, C365S145000, C365S158000, C365S170000
Reexamination Certificate
active
06940085
ABSTRACT:
A memory structure that includes a first electrode, a second electrode, a third electrode, a control element disposed between the first electrode and the second electrode, and a memory storage element disposed between the second electrode and the third electrode. At least one of the control element and memory storage element is protected from contamination by at least one of the first electrode, second electrode and third electrode.
REFERENCES:
patent: 3271591 (1961-09-01), Ovshinsky
patent: 3530441 (1970-09-01), Ovshinsky
patent: 3641516 (1972-02-01), Castrucci et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4599705 (1986-07-01), Holmberg et al.
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 5309392 (1994-05-01), Ootsuka et al.
patent: 5335219 (1994-08-01), Ovshinsky et al.
patent: 5374832 (1994-12-01), Tung et al.
patent: 5449947 (1995-09-01), Chen et al.
patent: 5534712 (1996-07-01), Ovshinsky et al.
patent: 5572050 (1996-11-01), Cohen
patent: 5625220 (1997-04-01), Liu et al.
patent: 5659500 (1997-08-01), Mehrad
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: 5821558 (1998-10-01), Han et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5942777 (1999-08-01), Chang
patent: 6002607 (1999-12-01), Dvir
patent: 6026017 (2000-02-01), Wong et al.
patent: 6033955 (2000-03-01), Kuo et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6111302 (2000-08-01), Zhang et al.
patent: 6185121 (2001-02-01), O'Neill
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6351406 (2002-02-01), Johnson et al.
patent: 6541792 (2003-04-01), Tran et al.
patent: 2001/0011776 (2001-08-01), Igarashi et al.
patent: 2001/0055838 (2001-12-01), Walker et al.
Victor W.C. Chan et al., “Multiple Layers of CMOS Inegrated Circuits Using Recrystalized Silicon Film” IEEE Electron Device Letters, V. 22, No. 2 (Feb. 2001) pp. 77-79.
Thomas H. Lee, “A Vertical Leap for Microchips,” Scientific American, Jan. 2002, pp. 53-59.
Esmat Hamdy et al., “Dielectric based antifuses for logic and memory ICs” IEEE International Electron Devices Meeting, IEDM 88 (Aug. 1988) pp. 786-789.
Chenming Hu, “Interconnect devices for field programmable gate array.” IEEE International Electron Devices Meeting, IEDM 92 (Apr. 1992) pp. 591-594.
Jonathan Green et al., “Antifuse Field Programmable Gate Arrays” Proc. IEEE vol. 81 No. 7 (Jul. 1993), pp. 1042-1056.
Vivek D. Kulkarni et al. “Patterning of Submicron Metal Features and Pillars in Multilevel Metalization” J. Electrochem. Soc. vol. 135 No. 12 (Dec. 1988) pp. 3094-3098.
Fricke Peter
Koll Andrew
Lazaroff Dennis M.
Van Brocklin Andrew L.
Hewlett-Packard Development Company, I.P.
Landau Matthew C
Thomas Tom
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