Memory structure with multiple integrated memory array portions

Details Memory structure with multiple integrated memory array portions Memory structure with multiple integrated memory array portions

1994-03-30

1997-02-18

Brier, Jeffery

Computer graphics processing and selective visual display system

Display peripheral interface input device

Light pen for fluid matrix display panel

G09G 506

Patent

active

056045182

ABSTRACT:
An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.

REFERENCES:
patent: 4769632 (1988-09-01), Work et al.
patent: 5228120 (1993-07-01), Farr et al.
patent: 5446482 (1995-08-01), Van Aken et al.
patent: 5488393 (1996-01-01), Wood et al.

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